1. Field of the Invention
The present invention pertains to the field of computer system buses. More particularly, this invention relates to the field of maintaining cache consistency in a multi-agent computer system.
2. Background
The speed and performance of modern computer systems is ever-increasing. One aspect of these advancements is the increasing use of high-speed cache memories. In many modern computer systems, multiple agents may reside on a single bus, each of which may have its own, individual high-speed cache.
The implementations of these caches vary, however each generally attempts to operate efficiently with both the latest advances in microprocessor technology as well as other agents residing on the bus, such as I/O devices. For example, some agents on the bus may be capable of performing accesses which take advantage of the full size of a cache line, whereas other agents may only be capable of performing accesses which use a portion of a cache line. Thus, computer systems must efficiently manage writing to a portion of a cache line which has been modified within the cache of another agent, i.e., a partial write data transfer to a modified cache line, while at the same time efficiently managing other cache line requests.
Additionally, in computer systems with multiple caches, cache consistency must be maintained in order to ensure proper system behavior. Cache consistency refers to all caches agreeing on which cache(s), or memory, has the most recent version of any particular cache line. One method of maintaining cache consistency includes a modified dirty (altered) bit associated with each cache line. This bit indicates whether the data contained in the cache is more recent than the data in main memory.
When a new memory transaction over the bus begins, all memory and caching agents participate in order to complete the transaction and maintain cache consistency. By maintaining cache consistency, all agents know whether their copy of the data is dirty, clean, or invalid.
One solution to the cache consistency problem utilizes a three-transaction, or three-phase, solution. For example, in a partial memory write data transaction to a writeback memory space, the agent making the request to memory issues the request in the first phase. Another agent on the bus, the snooping agent, which has a modified copy of the cache line corresponding to the request asserts a signal indicating this. In response to this signal, the memory unit, such as a memory controller connected to a main memory, issues a back-off signal. The requesting agent receives this back-off signal and knows it must wait to reinitiate the write request.
In phase two, the snooping agent knows from phase one that another agent desires access to the modified cache line, so the snooping agent issues a write operation of the cache line to the memory unit. Thus, main memory is updated with the most recent version of the cache line. In phase three, the memory unit releases the back-off signal to the requesting processor and the requesting processor is allowed to re-try the request. When the request is re-tried, the most recent version is in main memory and the request is successful (assuming no other agent has modified the cache line in its cache in the meantime).
While this three-phase solution is effective, it is not efficient in a pipelined environment due to the requirement of three transactions to successfully complete the request. Therefore, it would be advantageous to provide a mechanism that maintains cache consistency, while at the same time efficiently performing memory transactions to modified cache lines. The present invention provides such a solution.
In modern computer systems, the importance of system speed is ever-increasing. Thus, while this three-phase solution is effective, it is not efficient in a pipelined environment due to the requirement of three transactions to successfully complete the request. Therefore, it would be advantageous to provide a mechanism that maintains cache consistency, while at the same time efficiently performs memory transactions to modified cache lines. The present invention provides such a solution.
Furthermore, as microprocessors become smaller and smaller, efficient use of a limited amount of space is becoming increasingly important. Thus, it would be advantageous to provide a system which maintains cache consistency while employing a minimal amount of logic complexity.
Additionally, many modern computer systems utilize multiple processing agents, each of which may have its own cache. The number of processing agents, as well as the existence of multiple processing agents, varies. Thus, it would be advantageous to provide a versatile system which supports the insertion of multiple processors with a minimal amount of additional logic and expense. The present invention provides such a solution.